A conflict-free memory banking architecture for fast VOQ packet buffers

Routers and switches operating at high link rate require large and fast packet buffers. In many cases the buffers store cells from different queues which are requested by an arbiter. Such buffers can be built with slow but low cost DRAM coupled with fast but expensive SRAM. The heads and tails of the queues reside in SRAM, while the rest of the queues are stored in DRAM. Periodically a Memory Management Algorithm requests the transfer of a group of cells of a given queue between DRAM and SRAM. In this paper we propose a memory architecture that exploits memory bank organization in order to achieve conflict-free access. This leads to a reduction of the granularity of DRAM accesses, resulting in a decrease of storage capacity needed by the SRAM. We carry out an analysis giving the values of the system parameters that guarantee zero miss conditions. Moreover, a technological study of the system implementation shows that, confronted with previous designs [1], [2], our organization gives better results for area, access times, latency, and maximum number of queues.